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FEATURES Single +5 V Supply Transmit Channel On-Chip GMSK Modulator Two 10-Bit D/A Converters Analog Reconstruction Filters Power-Down Mode Receive Channel Two Sigma-Delta A/D Converters FIR Digital Filters On-Chip Offset Calibration Power-Down Mode 3 Auxiliary D/A Converters Power-Down Modes On-Chip Voltage Reference Low Power 44-Lead PQFP APPLICATIONS GSM PCN
LC2MOS GSM Baseband I/O Port AD7002
GENERAL DESCRIPTION
The AD7002 is a complete low power, two-channel, input/ output port with signal conditioning. The device is used as a baseband digitization subsystem, performing signal conversion between the DSP and the IF/RF sections in the Pan-European telephone system (GSM). The transmit path consists of an onboard digital modulator, containing all the code necessary for performing Gaussian Minimum Shift Keying (GMSK), two high accuracy, fast DACs with output reconstruction filters. The receive path is composed of two high performance sigma-delta ADCs with digital filtering. A common bandgap reference feeds the ADCs and signal DACs. Three control DACs (AUX DAC1 to AUX DAC3) are included for such functions as AFC, AGC and carrier signal shaping. In addition, AUX FLAG may be used for routing digital control information through the device to the IF/RF sections. As it is a necessity for all GSM mobile systems to use the lowest power possible, the device has power-down or sleep options for all sections (transmit, receive and auxiliary). The AD7002 is housed in 44-lead PQFP (Plastic Quad Flatpack).
FUNCTIONAL BLOCK DIAGRAM
DVDD DGND AV DD AGND
Tx SLEEP 10-BIT DAC GMSK PULSE SHAPING ROM Tx CLK 10-BIT DAC 4TH ORDER BESSEL LOW-PASS FILTER 4TH ORDER BESSEL LOW-PASS FILTER
AD7002
I Tx
Tx DATA
Q Tx REFERENCE OUTPUT BUFFER REF OUT
THREE-STATE ENABLE Rx CLK Rx DATA (I DATA) Rx SYNC I/Q (Q DATA) RATE MODE AUX DATA AUX CLK AUX LATCH Rx SLEEP1 Rx SLEEP2 9-BIT DAC 10-BIT DAC 8-BIT DAC 16-BIT SHIFT REGISTER RECEIVE CHANNEL SERIAL INTERFACE
2.5V REFERENCE
I CHANNEL DIGITAL FIR FILTER OFFSET REGISTER
- MODULATOR
SWITCH-CAP FILTER
I Rx
OFFSET REGISTER Q CHANNEL DIGITAL FIR FILTER - MODULATOR SWITCH-CAP FILTER Q Rx
AUX DAC 1
AUX DAC 2
AUX DAC 3
AUX FLAG
CAL
CLK2
CLK1
MZERO
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997
AD7002-SPECIFICATIONS1 T = T
Parameter ADC SPECIFICATIONS Resolution Signal Input Span Sampling Rate Output Word Rate Accuracy Integral Differential2 Bias Offset Error Input Resistance (DC) Input Capacitance Dynamic Specifications Dynamic Range Signal to (Noise+Distortion) Gain Error Gain Match Between Channels Filter Settling Time Frequency Response 0 kHz-100 kHz 110 kHz 122 kHz 200 kHz 400 kHz-6.5 MHz Absolute Group Delay Group Delay Between Channels (0 kHz-120 kHz) Coding Power-Down Option TRANSMIT DAC SPECIFICATIONS Resolution Number of Channels Update Rate DC Accuracy Integral Differential Output Signal Span Output Signal Full-Scale Accuracy Offset Error I Tx & Q Tx Gain Matching Absolute Group Delay Group Delay Linearity (0 kHz-120 kHz) Phase Matching Between Channels GMSK Spectrum Mask3 100 kHz 200 kHz 250 kHz 400 kHz 0.6 MHz 4.3 MHz 6.5 MHz GMSK Phase Trajectory Error3 Maximum Phase Effect Instance3 Output Impedance I Tx Q Tx GMSK ROM Power-Down Option
(AVDD = +5 V 10%; DVDD = +5 V 10%; AGND = DGND = 0 V, fCLK1 = fCLK2 = 13 MHz; A MIN to TMAX, Rx SLEEP1 = Rx SLEEP2 = Tx SLEEP = DVDD, unless otherwise noted)
Units Bits Volts MSPS kHz kHz LSB typ LSB max LSB typ k typ pF typ dB typ dB min dB max dB max s typ dB max dB max dB max dB max dB max s typ ns typ Rx SLEEP = VDD, Independent of Transmit Bits MSPS LSB typ LSB typ Volts dB max mV max dB max s typ ns typ typ dB min dB min dB min dB min dB min dB min dB min rms max peak max s typ typ typ Contains GMSK Coding, Four-Bit Impulse Response Tx SLEEP = VDD, Independent of Receive -2- REV. B Rx SLEEP = VDD, Tx SLEEP = 0 V 16 Oversampling of the Bit Rate After External Calibration; MZERO Low After Internal Calibration; MZERO High Test Conditions/Comments Rx SLEEP = 0 V, Tx SLEEP = VDD Biased on VREF (2.5 V) RATE 0 RATE 1
AD7002A 12 VREF/2 13 270.8 541.7 1 0 6.5 8 300 10 64 62 0.5 0.15 47 0.05 -0.8 -3.0 -66 -72 23 5 Twos Complement Yes 10 2 4.33 0.7 1.0 VREF/2 1 25 0.15 10 30 0.5 -3 -32 -35 -63 -71 -63 -63 2 6 9 120 120 Yes Yes
Input Frequency = 67.7 kHz
Input Frequency = 67.7 kHz, w.r.t. 2.5 V Input Frequency = 67.7 kHz
Centered on VREF Nominal (100 k/20 pF Load) w.r.t. 2.5 V 10 0000 0000 Loaded to DAC Measured at 67.7 kHz Each Channel, 10 kHz < FOUT < 100 kHz Generating 67.7 kHz Sine Waves
AD7002
Parameter AUXILIARY DAC SPECIFICATIONS Resolution DC Accuracy Integral Differential Offset Error Gain Error LSB Size Output Signal Span Output Impedance AD7002A AUX1 9 2 1 2 4 4.88 0 to VREF 10 8 Binary Yes AUX2 10 2 1 4 4 2.44 0 to VREF 10 8 Binary Yes AUX3 8 1 1 1 2 9.77 0 to VREF 10 8 Binary Yes Units Bits LSB max LSB max LSB max LSB max mV typ Volts k max k typ Power-Down Is Implemented by Loading All 1s or All 0s V min/V max V typ ppm/C typ mV max typ V min V max A max pF max V min V max V min/V max V min/V max mA max mA max mA typ mA max mA typ mA max |IOUT| 200 A |IOUT| 1.6 mA RL = 100 k, CL = 1 nF RL = 100 k, CL = 1 nF Test Conditions/Comments
Guaranteed Monotonic
Unloaded Output AUX DACs Have Unbuffered Resistive Outputs
Coding Power-Down REFERENCE SPECIFICATIONS REFOUT, Reference Output REFOUT, Reference Output @ +25C Reference Temperature Coefficient Reference Variation4 Output Impedance LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD IDD All Sections Active ADC and Auxiliary Paths Active5 Transmit DAC and AUX Paths Active6 Auxiliary Path only Active5, 6, 7
2.4/2.6 2.5 100 10 60 VDD - 0 9 0.9 10 10 4.0 0.4 4.5/5.5 4.5/5.5 30 18 15 14 11 2
Tx SLEEP = VDD Rx SLEEP1 = Rx SLEEP2 = VDD Tx SLEEP = Rx SLEEP1 = Rx SLEEP2 = VDD
NOTES 1 Operating temperature range: A Version: -40C to +85C. 2 Unmeasurable: sigma-delta conversion is inherently free of differential nonlinearities. 3 See terminology. 4 Change in reference voltage due to a change in Tx SLEEP or Rx SLEEP modes. 5 Measured while the digital inputs to the transmit interface are static. 6 Measured while the digital inputs to the receive interface are static. 7 Measured while the digital inputs to the auxiliary interface are static. Specifications subject to change without notice.
REV. B
-3-
AD7002
ABSOLUTE MAXIMUM RATINGS 1 (TA = +25C unless otherwise noted) TERMINOLOGY Absolute Group Delay
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital Input Voltage to DGND . . . . -0.3 V to DVDD + 0.3 V Analog Input Voltage to AGND . . . . -0.3 V to AVDD + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . . 10 mA Operating Temperature Range Industrial Plastic (A Version) . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . +300C Power Dissipation (Any Package) to +75C . . . . . . . 450 mW Derates Above +75C by . . . . . . . . . . . . . . . . . . . . 10 mW/C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at those or any other conditions above those listed in the operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
Absolute group delay is the rate of change of phase versus frequency, d/df. It is expressed in microseconds.
Bias Offset Error
This is the offset error (in LSBs) in the ADC section.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the DAC or ADC.
Dynamic Range
Dynamic Range is the ratio of the maximum output signal to the smallest output signal the converter can produce (1 LSB), expressed logarithmically, in decibels (dB = 20log10 (ratio)). For an N-bit converter, the ratio is theoretically very nearly equal to 2N (in dB, 20Nlog10(2) = 6.02N). However, this theoretical value is degraded by converter noise and inaccuracies in the LSB weight.
Full-Scale Accuracy
PIN DESCRIPTION
36 AUX DAC2 35 AUX DAC3 34 AUX DAC1 40 REFOUT
This is the measure of the ADC full-scale error after the offset has been adjusted out.
Gain Error
This is a measure of the output error between an ideal DAC and the actual device output with all ls loaded after offset error has been adjusted out and is expressed in LSBs. In the AD7002, gain error is specified for the auxiliary section.
Gain Matching Between Channels
33 AUX FLAG 32 AUX LATCH 31 AUX CLK 30 AUX DATA 29 MZERO 28 NC 27 Rx SLEEP1 26 TEST2 25 NC 24 Rx SLEEP2 23 CAL
AMPLITUDE - dB
43 TEST4
38 AGND
42 Q Rx
41 I Tx
39 Q Tx
44 I Rx
37 AV DD
Tx SLEEP 1 Tx DATA 2 Tx CLK 3 DVDD 4 DGND 5 NC 6 CLK1 7 TEST1 8 NC 9 NC 10 CLK2 11
PIN 1 IDENTIFIER
This is the gain matching between the ITx and QTx channel and is expressed in dBs.
GMSK Spectrum Mask
AD7002 PQFP
TOP VIEW (Not to Scale)
This is the combined output spectrum of the I and Q analog outputs when transmitting a random sequence of data bits on the AD7002 transmit channel.
-3
-32 -35
MODE 13
3-STATE ENABLE 22
NC 17 Rx DATA (IDATA) 18
I/Q (QDATA) 19
Rx SYNC 20
Rx CLK 21
RATE 12
TEST3 14 DVDD 15
DGND 16
-63 -71 -71
-63
-63
NC = NO CONNECT
100
200 250
400
600 FREQUENCY - kHz
1800
4300
6500
ORDERING GUIDE
AD7002 Transmit GMSK Spectrum Mask
Model
Temperature Range
Package Description
Package Option
AD7002AS -40C to +85C Plastic Quad Flatpack S-44
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7002 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. B
AD7002
GMSK Phase Trajectory Error Offset Error
This is a measure of the phase error between the transmitted phase of an ideal GMSK modulator and the actual phase transmitted by the AD7002, when transmitting a random sequence of data bits. It is specified as a peak phase error and also as an rms phase error.
Group Delay Linearity
This is the amount of offset, w.r.t. VREF in the transmit DACs and the auxiliary DACs and is expressed in mVs for the Transmit section and in LSBs for the Auxiliary section.
Output Impedance
This is a measure of the drive capability of the auxiliary DAC outputs and is expressed in ks.
Output Signal Span
The group delay linearity, or differential group delay, is the group delay over the full band relative to the group delay at one particular frequency. The reference frequency for the AD7002 is 1 kHz.
Group Delay Between Channels
This is the output signal range for the Transmit Channel section and the Auxiliary DAC section. For the transmit channel the span is 1.25 volts centered on 2.5 volts, and for the Auxiliary DAC section it is 0 to +VREF.
Output Signal Full-Scale Accuracy
This is the difference between the group delay of the I and Q channels and is a measure of the phase matching characteristics of the two.
Integral Nonlinearity
This is the accuracy of the full-scale output (all 1s loaded to the DACs) on each transmit channel measured w.r.t. 25 V and is expressed in dBs.
Phase Matching Between Channels
This is the maximum deviation from a straight line passing through the endpoints of the DAC or ADC transfer function.
Maximum Phase Effect Instance
This is the time at which a transmitted data bit will have its maximum phase change at the ITx and QTx outputs (see figure). This time includes the delay in the GMSK modulator and in the Analog low-pass filters. Maximum phase effect instance is measured from the Tx CLK falling edge, which latches the data bit, to the ITx and QTx analog outputs.
90
This is a measure of the phase matching characteristics of the I and Q transmit channels. It is obtained by transmitting all ones and then measuring the difference between the actual phase shift between the I and Q outputs and the ideal phase shift of 90.
Sampling Rate
This is the rate at which the modulators on the receive channels sample the analog input.
Settling Time
TRANSMITTED PHASE FOR ONE DATA BIT
This is the digital filter settling time in the AD7002 receive section. On initial power-up, or after returning from the sleep mode, it is necessary to wait this amount of time to obtain useful data.
Signal Input Span
45
The input signal range for the I and Q channels is biased about VREF. It can go 1.25 volts about this point.
Signal to (Noise + Distortion) Ratio
0
9s
DATA BIT CLOCKED IN BY TxCLK
MAXIMUM PHASE EFFECT INSTANT
Transmit Channel Maximum Phase Effect Instance
Output Rate
This is the rate at which data words are made available at the Rx DATA pin (Mode 0) or the IDATA and QDATA pins (Mode 1). There are two rates, depending on whether the device is operated in RATE0 or RATE1.
This is the measured ratio of signal-to-(noise + distortion) at the output of the receive channel. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise+distortion) ratio for a sine wave is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB
REV. B
-5-
AD7002 INPUT CLOCK TIMING1 (AV
Parameter t1 t2 t3 76 30 30
DD
= +5 V
10%; DVDD = +5 V
Units ns min ns min ns min
10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted)
Description CLK1, CLK2, AUX CLK Cycle Time CLK1, CLK2, AUX CLK High Time CLK1, CLK2, AUX CLK Low Time
Limit at TA = -40 C to +85 C
TRANSMIT SECTION TIMING
Parameter t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 10 20 24 t1 24 t1 + 80 48 t1 24 t1 24 t1 0 100 30 30 10 0 23 t1 10 10
(AVDD = +5 V 10%; DVDD = +5 V 10%; AGND = DGND = 0 V, fCLK1 = fCLK2 = 13 MHz; TA = TMIN to TMAX, unless otherwise noted)
Units ns min ns min ns min ns max ns ns ns ns min ns max ns max ns max ns min ns min ns max ns typ ns typ Description Tx SLEEP Hold Time Tx SLEEP Setup Time Tx CLK Active After CLK1 Rising Edge Following Tx SLEEP Low Tx CLK Cycle Time Tx CLK High Time Tx CLK Low Time Propagation Delay from CLK1 to Tx CLK Data Setup Time Data Hold Time Tx CLK to Tx SLEEP Asserted for Last Tx CLK Cycle2 Digital Output Rise Time3 Digital Output Fall Time3
Limit at TA = -40 C to +85 C
AUXILIARY DAC TIMING unless otherwise noted)
Parameter t16 t17 t18 t19 t20 t21 t22 Limit at TA = -40 C to +85 C 10 10 25 20 50 10 10
(AVDD = +5 V
10%; DVDD = +5 V
10%; AGND = DGND = 0 V, fAUX CLK = 13 MHz; TA = TMIN to TMAX,
Units ns min ns min ns min ns min ns max ns typ ns typ
Description AUX DATA Setup Time AUX DATA Hold Time AUX LATCH to SCLK Falling Edge Setup Time AUX LATCH to SCLK Falling Edge Hold Time AUX LATCH High to AUX FLAG Valid Delay Digital Output Rise Time Digital Output Fall Time
NOTES 1 Sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 t13 specifies a window, that Tx SLEEP should be asserted for the current Tx CLK to be the last prior to entering SLEEP mode. 3 Digital output rise and fall times specify the time required for the output to go between 10% and 90% of 5 V. Specifications subject to change without notice.
1.6mA
IOL
t1 t2
CLK1, CLK2, AUX CLK
TO OUTPUT PIN CL 15pF
+2.1V
t3
200A IOH
Figure 1. Clock Timing
Figure 2. Load Circuit for Timing Specifications
-6-
REV. B
AD7002 RECEIVE SECTION TIMING
Parameter t23 t24 t25 t26 32 t1 + t2 31 t1 + t2 t27 t1 2 t1 t28 25 90 t29 t30 t31 t32 t33 24 t1 12 t1 48 t1 24 t1 t34 t35 t36 t37 5 t1 + 5 5 10 10 ns max ns max ns max ns typ ns typ ns ns ns ns 25 30 10 30 20 t1 2 t1 ns min ns min ns min ns max ns min ns ns ns min ns min ns ns ns ns 0 25 0 39 t1 15 t1
1 (AVDD = +5 V
10%; DVDD = +5 V 10%; AGND = DGND = 0 V, fCLK1 = fCLK2 = 13 MHz; TA = TMIN to TMAX, unless otherwise noted)
Units ns min ns min ns min ns max ns max Description Rx SLEEP Hold Time After CLK1, CLK2 High Rx SLEEP Setup Time Before CLK1, CLK2 High Rx SYNC to Rx SLEEP Asserted2 RATE 0 RATE 1 Rx CLK Active After CLK1 Rising Edge Following Falling Edge of Rx SLEEP MODE 0 MODE 1 Rx CLK Cycle Time3 MODE 0 MODE 1 Rx CLK High Pulse Width MODE 0 MODE 1 Rx CLK Low Pulse Width MODE 0 MODE 1 Propagation Delay from CLK1, CLK2 High to Rx CLK High Rx SYNC Valid Prior to Rx CLK Falling Rx SYNC High Pulse Width MODE 0 MODE 1 Rx SYNC Cycle Time3 MODE 0 RATE 0 MODE 0 RATE 1 MODE 1 RATE 0 MODE 1 RATE 1 Rx DATA Valid After Rx CLK Rising Edge MODE 0 MODE 1 MODE 0 only, Propagation Delay from Rx CLK Rising Edge to I/Q Digital Output Rise Time4 Digital Output Fall Time4
Limit at TA = -40 C to +85 C
CALIBRATION AND CONTROL TIMING
Parameter t38 t39 t40 Limit at TA = -40 C to +85 C 25 608 t1 25
(AVDD = +5 V 10%; DVDD = +5 V 10%; AGND = DGND = 0 V, fAUX CLK = 13 MHz; TA = TMIN to TMAX, unless otherwise noted)
Units ns min ns min ns min Description SLEEP to CAL Setup Time CAL Pulse Width RATE, MODE or THREE-STATE ENABLE Setup Time
NOTES 1 Sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 t25 specifies a window, after Rx SYNC which marks the beginning of I data, that Rx SLEEP should be asserted for the subsequent IQ data pair to be last prior to entering SLEEP mode. 3 See Figure 2 for test circuit. 4 Digital output rise and fall times specify the time required for the output to go between 10% and 90% of 5 V. Specifications subject to change without notice.
REV. B
-7-
AD7002
CIRCUIT DESCRIPTION TRANSMIT SECTION
The transmit section of the AD7002 generates GMSK I and Q waveforms in accordance with GSM recommendation 5.04. This is accomplished by a digital GMSK modulator, followed by 10-bit DACs for the I and Q channels and on-chip reconstruction filters. The GMSK (Gaussian Minimum Shift Keying) digital modulator generates I and Q signals, at 16 oversampling, in response to the transmit data stream. The I and Q data streams drive 10-bit DACs, which are filtered by on-chip Bessel low-pass filters.
GMSK PULSE SHAPING ROM 16x OVERSAMPLING COSINE LOOK UP TABLE 10 IDATA
16 times the transmit data rate. The transmit data (Tx DATA) is first differentially encoded as specified by GSM 5.04 section 2.3 (Table I). The GMSK modulator generates 10-bit I and Q waveforms (Inphase and Quadrature), in response to the encoded data, which are loaded into the 10-bit I and Q transmit DACs. The Gaussian filter, in the GMSK modulator, has an impulse response truncated to four data bits. When the transmit section is brought out of sleep mode (Tx SLEEP low), the modulator is reset to a transmitting all 1s state. When Tx SLEEP is asserted (Tx SLEEP high), the transmit section powers down, with the I Tx and Q Tx outputs connected to VREF through a nominal impedance of 80 k.
Reconstruction Filters
Tx DATA
DIFFERENTIAL ENCODER
GUASSIAN FILTER
INTEGRATOR SINE LOOK UP TABLE 10 QDATA
Figure 3. GMSK Functional Block Diagram
Table I. Truth Table for the Differential Encoder
Tx DATAi 0 0 1 1
Tx DATAi-1 0 1 0 1
Differentially Encoded Data +1 -1 -1 +1
The reconstruction filters smooth the DAC output signals, providing continuous time I and Q waveforms at the output pins. These are Bessel low-pass filters with a cutoff frequency of approximately 300 kHz. Figure 5 shows a typical transmit filter frequency response, while Figure 6 shows a typical plot of group delay versus frequency. The filters are designed to have a linear phase response in the passband and due to the reconstruction filters being on-chip, the phase mismatch between the I and Q transmit channels is kept to a minimum.
Transmit Section Digital Interface
GMSK Modulator
Figure 3 shows the functional block diagram of the GMSK modulator. This is implemented using control logic with a ROM look up table, to generate I and Q data samples at
Figure 4 shows the timing diagram for the transmit interface. Tx SLEEP is sampled on the falling edge of CLK1. When Tx SLEEP is brought low, Tx CLK becomes active after 24 master clock cycles. Tx CLK can be used to clock out the transmit data from the ASIC or DSP on the rising edge and Tx DATA is clocked into the AD7002 on the falling edge of Tx CLK. When Tx SLEEP is asserted the transmit section is immediately put into sleep mode, disabling Tx CLK and powering down the transmit section.
CLK1 (I) t4 t5 Tx SLEEP (I) t6 Tx CLK (O) t8 t11 Tx DATA (I) VALID DATA NOTE: (I) = DIGITAL INPUT; (0) = DIGITAL OUTPUT t9 t12 VALID DATA VALID DATA t7 t10 t13
Figure 4. Transmit Section Timing Diagram
-8-
REV. B
AD7002
0.0 -5.0 -10.0 -15.0 -20.0
GAIN - dB
GROUP DELAY - s
0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10
-25.0 -30.0 -35.0 -40.0 -45.0 -50.0 -55.0 -60.0 1.00 + 03 1.00 + 04 1.00 + 05 FREQUENCY - Hz 1.00 + 06 1.00 + 07
0.00 1.00 + 03
1.00 + 04
1.00 + 05 FREQUENCY - Hz
1.00 + 06
1.00 + 07
Figure 5. Transmit Filter Frequency Response
Figure 6. Transmit Filter Group Delay
GMSK SPECTRUM TEST, DC TO 6.4MHz. FREQUENCY RESOLUTION: 30.1514kHz 0 -10 -20
MAGNITUDE - dB
MAGNITUDE - dB
10 0 -10 -20 -30 -40 GMSK MASK -50 -60
-30 -40 -50 -60 -70 -80 -90 0 8.0 1.6 2.4 3.2 4.0 4.8 5.6 6.4 FREQUENCY - MHz
-70 GMSK SPECTRUM -80 -90 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY - kHz
Figure 7. Typical Spectrum Plot of the Transmit Channel When Transmitting Random Data (0 MHz to 6.4 MHz)
Figure 8. Typical Spectrum Plot of the Transmit Channel When Transmitting Random Data (0 MHz to 1 MHz)
PEAK PHASE TRAJECTORY ERROR = 1.56 RMS PHASE TRAJECTORY ERROR = 0.79 PEAK PHASE TRAJECTORY ERROR - Degrees 5 4 3
I2 + Q2 - Voltage
1.27
1.26
2 1 0 -1 -2 -3 -4 -5
1.25
1.24
1.23
1.22
1.21
Figure 9. Typical Plot of the Transmit Phase Trajectory Error
Figure 10. Typical Plot of the Composite Vector Magnitude
REV. B
-9-
AD7002
RECEIVE SECTION
The receive section consists of I and Q receive channels, each comprised of a simple switched capacitor filter followed by a 12-bit sigma-delta ADC. The data is available on a flexible serial interface, interfacing easily to most DSPs. The data can be configured to be one of two formats and is also available at two sampling rates. Onboard digital filters, which form part of the sigma-delta ADCs, also perform critical system level filtering. Their amplitude and phase response characteristics provide excellent adjacent channel rejection. The receive section is also provided with a low power sleep mode to place the receive section on standby between receive bursts, drawing only minimal current.
Switched Capacitor Input
The digital filter that follows the modulator removes the large out-of-band quantization noise (Figure 12c), while converting the digital pulse train into parallel 12-bit-wide binary data. The 12-bit I and Q data is made available, via a serial interface, in a variety of formats.
a.
QUANTIZATION NOISE BAND OF INTEREST FS/2 3.25 MHz
b.
BAND OF INTEREST
NOISE SHAPING FS/2 3.25 MHz
The receive section analog front end is sampled at 13 MHz by a switched capacitor filter. The filter has a zero at 6.5 MHz as shown in Figure 11a. The receive channel also contains a digital low-pass filter (further details are contained in the following section) that operates at a clock frequency of 6.5 MHz. Due to the sampling nature of the digital filter, the pass band is repeated about the operating clock frequency and at multiples of the clock frequency (Figure 11b). Because the first null of the switched capacitor filter coincides with the first image of the digital filter, this image is attenuated by an additional 30 dBs (Figure 11c), further simplifying the external antialiasing requirements.
a.
0dB
c.
BAND OF INTEREST
DIGITAL FILTER CUTOFF FREQUENCY = 122 kHz FS/2 3.25 MHz
Figure 12. Sigma-Delta ADC
DIGITAL FILTER
FRONT-END ANALOG FILTER TRANSFER FUNCTION
6.5
13
19.5
MHz
The digital filters used in the AD7002 receive section carry out two important functions. First, they remove the out-of-band quantization noise that is shaped by the analog modulator. Second, they are also designed to perform system level filtering, providing excellent rejection of the neighboring channels. Digital filtering has certain advantages over analog filtering. First, since digital filtering occurs after the A/D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Second, the digital filter combines low passband ripple with a steep rolloff, while also maintaining a linear phase response. This is very difficult to achieve with analog filters. Analog filtering can, however, remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator, even though the average value of the signal is within limits. To alleviate this problem, the AD7002 has overrange headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 100 mV.
Filter Characteristics
b.
0dB
DIGITAL FILTER TRANSFER FUNCTION
6.5
13
19.5
MHz
c.
0dB -30dB MAX 6.5 13 19.5 MHz
SYSTEM FILTER TRANSFER FUNCTION
Figure 11. Switched Capacitor Input
SIGMA-DELTA ADC
The AD7002 receive channels employ a sigma-delta conversion technique that provides a high resolution 12-bit output for both I and Q channels, with system filtering being implemented on-chip. The output of the switched capacitor filter is continuously sampled at 6.5 MHz (master clock/2) by a charge balanced modulator, and is converted into a digital pulse train whose duty cycle contains the digital information. Due to the high oversampling rate, which spreads the quantization noise from 0 MHz to 3.25 MHz (FS/2), the noise energy contained in the band of interest is reduced (Figure 12a). To reduce the quantization still further, a high order modulator is employed to shape the noise spectrum, so that most of the noise energy is shifted out of the band of interest (Figure 12b).
The digital filter is a 288-tap FIR filter, clocked at half the master clock frequency. The frequency response is shown in Figure 14. The 3 dB point is at 122 kHz. Due to the low pass nature of the receive filters, there is a settling time associated with step input functions. Output data will not be meaningful until all the digital filter taps have been loaded with data samples taken after the step change. Hence the AD7002 digital filters have a settling time of 44.7 s (288 2 t1). When coming out of sleep, the digital filter taps are reset. Hence data, initially generated by the digital filters, will not be correct. Not until all 288 taps have been loaded with meaningful data REV. B
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AD7002
from the analog modulator, will the output data be correct. The analog modulator, on coming out of sleep, will generate meaningful data after 21 master clock cycles.
01...111 01...110
convenient or necessary. Only the digital result following the fall of CAL will be loaded into each offset register. After CAL falls, normal operation resumes immediately.
10.00 0.00 -10.00 -20.00 -30.00 -40.00 GAIN - dB -50.00 -60.00 -70.00 -80.00 -90.00
00...001 ADC CODE 00...000 11...111 11...110
-100.00 -110.00
10...001 10...000 -VFULLSCALE VREF VIN , INPUT VOLTAGE +VFULLSCALE
-120.00 -130.00 -140.00 0 100 200 300 400 500 600 700 FREQUENCY - kHz 800 900 1000
Figure 13. ADC Transfer Function for I and Q Receive Channels
Calibration
Figure 14. Digital Filter Frequency Response
Included in the digital filter is a means by which receive signal offsets may be calibrated out. Calibration can be effected through the use of the CAL and MZERO pins. Each channel of the digital low-pass filter section has an offset register. The offset register can be made to contain a value representing the dc offset of the preceding analog circuitry. In normal operation, the value stored in the offset register is subtracted from the filter output data before the data appears on the serial output pin. By so doing, the dc offset is cancelled. In each channel the offset register is cleared (twos complement zero) when CAL is high and becomes loaded with the first digital filter result after CAL falls. This result will be a measure of the channel dc offset if the analog channel is switched to zero prior to CAL falling. Time must be provided for the analog circuitry and the digital filter to settle after the analog circuitry is switched to zero and before CAL falls. The offset register will then be loaded with the proper representation of the dc offset. CAL must be high for more than 608 master clock cycles (CLK1, CLK2). If the analog channels are switched to zero coincident with CAL rising, this time is also sufficient to satisfy the settling time of the analog sigma-delta modulators and the digital filters. CAL may be held high for an unlimited time if
The offset registers are static and retain their contents even during sleep mode (Rx SLEEP1 and Rx SLEEP2 high). They need only be updated if drifts in the analog dc offsets are experienced or expected. However, on initial application of power to the digital supply pins the offset registers may contain grossly incorrect values and, therefore, calibration must be activated at least once after power is applied even if the facility of calibration is not regularly used.
Table II. Truth Table for the MODE and RATE Pins
MODE 0 0 1 1
RATE 0 1 0 1
Data Format IQ Data IQ Data I Data I Data I/Q I/Q Q Data Q Data
Output Word Rate 270.8 kHz 541.7 kHz 270.8 kHz 541.7 kHz
The MZERO pin can be used to zero the sigma-delta modulators if calibration of preceding analog circuitry is not required. Each analog modulator has an internal analog multiplexer controlled by MZERO. With MZERO low, the modulator inputs are connected to the I Rx and Q Rx pins for normal operation. With MZERO high, both modulator inputs are connected to the VREF pin, which is analog ground for the modulators. If calibration of external analog circuitry is desired, MZERO should be kept low during the calibration cycle.
Rx SLEEP1 Rx SLEEP2
t38
CAL
t 39
t40
RATE, MODE, THREE- STATE CONTROL
Figure 15. Calibration and Control Timing Diagram
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AD7002
The offset registers have enough resolution to hold the value of any dc offset between 5 V. However, the performance of the sigma-delta modulators will degrade if full scale signals with more than 100 mV of offset are experienced. If large offsets are present, these can be calibrated out, but signal excursions from the offsets should be limited to keep the I Rx and Q Rx voltages within 1.35 V of VREF.
Receive Section Digital Interface
Rx DATA pin, but here the output word rate is reduced to 270.8 kHz, this being equal to master clock (CLK1, CLK2) divided by 48. Once the receive section is brought out of sleep mode, (after 56 master clock cycles) the Rx CLK output becomes active and generates an Rx SYNC framing pulse on the first Rx CLK. This is followed by 12 continuous clock cycles during which the I data is shifted out on the Rx DATA pin. Following this the Rx CLK remains high for 11 master clock cycles before clocking out the Q data in exactly the same manner. Rx DATA is valid on the falling edge of Rx CLK with the I/Q pin indicating whether Rx DATA is I data or Q data.
MODE 1 RATE I Interface
A flexible serial interface is provided for the AD7002 receive section. Four basic operating modes are available. Table II shows the truth table for the different serial modes available. The MODE pin determines whether the I and Q serial data is made available on two separate pins (MODE 1) or combined onto a single output pin (MODE 0). The RATE pin determines whether I and Q receive data is provided at 541.7 kHz (RATE 1) or at 270.8 kHz (RATE 0). When the receive section is put into sleep mode, by bringing Rx SLEEP1 and Rx SLEEP2 high, the receive interface will complete the current IQ cycle before entering into a low power sleep mode.
MODE 0 RATE I Interface
Figure 18 shows the timing for MODE 1 RATE 1 receive digital interface. MODE 1 RATE 1 gives an output word rate of 541.7 kHz, but I and Q data are transferred on separate pins. I data is shifted out on Rx DATA (IDATA) pin and Q data is shifted out on the I/Q (QDATA) pin. RATE 1 selects an output word rate of 541.7 kHz (this is equal to the master clock divided by 24). When the receive section is brought out of sleep mode, by bringing Rx SLEEP1 and Rx SLEEP2 low (after 32 master clock cycles), the Rx CLK output will continuously shift out I and Q data, on separate pins. Rx SYNC provides a framing signal used to indicate the beginning of an I or Q, 12-bit data word that is valid on the next falling edge of Rx CLK. On coming out of sleep, Rx SYNC goes high one clock cycle before the beginning of I data, and subsequently goes high in the same clock cycle as the I and Q LSBs. It takes 24 Rx CLKs (excluding the first framing pulse) to complete a single IQ cycle. IDATA and QDATA are valid on the falling edge of Rx CLK and are clocked out MSB first.
MODE I RATE 0 Interface
The timing diagram for the MODE 0 RATE 1 receive interface is shown in Figure 16. It can be used to interface to DSP processors requiring only one serial port. When using MODE 0, the serial data is made available on the Rx DATA pin, with the I/Q pin indicating whether the 12-bit word being clocked out is an I sample or a Q sample. Although the I data is clocked out before the Q data, internally both samples are processed together. RATE 1 selects an output word rate of 541.7 kHz, which is equal to the master clock (CLK1, CLK2) divided by 24. When the receive section is brought out of sleep mode, by bringing Rx SLEEP1 and Rx SLEEP2 low, (after 32 master clock cycles) the Rx CLK output will continuously shift out I and Q data, always beginning with I data. Rx SYNC provides a framing signal used to indicate the beginning of an I or Q, 12-bit data word that is valid on the next falling edge of Rx CLK. On coming out of sleep, Rx SYNC goes high one clock cycle before the beginning of I data, and subsequently goes high in the same clock cycle as the last bit of each 12-bit word (both I and Q). Rx DATA is valid on the falling edge of Rx CLK and is clocked out MSB first, with the I/Q pin indicating whether Rx DATA is I data or Q data.
MODE 0 RATE 0 Interface
Figure 19 shows the receive timing diagram when MODE 1 RATE 0 is selected. MODE 1 RATE 0, again I and Q data are transferred on separate pins. I data is shifted out on Rx DATA (IDATA) pin and Q data is shifted out on the I/Q (QDATA) pin. The output word rate is reduced to 270.8 kHz, this equal to master clock (CLK1, CLK2) divided by 48. Once the receive section is brought out of sleep mode, and after 56 master clock cycles, the Rx CLK output becomes active and generates an Rx SYNC framing pulse on the first Rx CLK. This is followed by 12 continuous clock cycles during which both the I and Q data is shifted out on IDATA and QDATA pins. Following this the Rx CLK remains high for 22 master clock cycles before clocking out the next IQ data pair.
Figure 17 shows the receive timing diagram when MODE 0, RATE 0 is selected. Again I and Q data are shifted out on the
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AD7002
CLK1, CLK2 (I)
t23 t24
Rx SLEEP1 (I) Rx SLEEP2 (I)
t 25
t26
Rx CLK (O)
t30
t27
t28
t31
Rx SYNC (O)
t29 t33
t34
Rx DATA (O)
I MSB I LSB Q MSB Q LSB I MSB I LSB
t32
Q MSB Q LSB
t35
I/Q (O)
t35
NOTE: (I) = DIGITAL INPUT; (O) = DIGITAL OUTPUT
Figure 16. MODE 0 RATE 1 Receive Timing
CLK1, CLK2 (I)
t23 t24
Rx SLEEP1 (I) Rx SLEEP2 (I)
t25
t26
Rx CLK (O)
t30
t27
t28
t31
Rx SYNC (O)
t33
t29
t34
Rx DATA (O)
I MSB I LSB Q MSB Q LSB
t32
I MSB I LSB Q MSB Q LSB
t35
I/Q (O)
t35
NOTE: (I) = DIGITAL INPUT; (O) = DIGITAL OUTPUT
Figure 17. MODE 0 RATE 0 Receive Timing
CLK1, CLK2 (I)
t23
Rx SLEEP1 (I) Rx SLEEP2 (I) Rx CLK (O)
t24 t26 t 31 t30 t27
t25
t28 t29
t33 t32
Rx SYNC (O)
I DATA (O)
t34
I MSB
I LSB
I MSB
I LSB
Q DATA (O)
t34
Q MSB
Q LSB
Q MSB
Q LSB
NOTE: (I) = DIGITAL INPUT; (O) = DIGITAL OUTPUT
Figure 18. MODE 1 RATE 1 Receive Timing
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AD7002
CLK1, CLK2 (I)
t23
Rx SLEEP1 (I) Rx SLEEP2 (I) Rx CLK (O)
t24 t26 t 31 t30 t27 t28
t25
t33 t34
I MSB I LSB
t29
Rx SYNC (O)
t32
I MSB I LSB
I DATA (O)
t34
Q DATA (O)
Q MSB Q LSB Q MSB Q LSB
NOTE: (I) = DIGITAL INPUT; (O) = DIGITAL OUTPUT
Figure 19. MODE 1 RATE 0 Receive Timing
AUXILIARY DACS
Three auxiliary DACs are provided for extra control functions such as automatic gain control, automatic frequency control or for ramping up/down the transmit power amplifiers during the beginning/end of a transmit burst. The three auxiliary DACs, AUX DAC1, AUX DAC2 and AUX DAC3, have resolutions of 9-, 10- and 8-bits, respectively. In addition to the three auxiliary DACs, the auxiliary section contains a digital output flag (AUX FLAG) with three-state control. Communication and sleep control of the auxiliary section is totally independent of either the transmit or receive sections. The AD7002 AUX DACs are voltage mode DACs, consisting of R-2R ladder networks (Figure 20 shows AUX DAC1 architecture), constructed from highly stable thin-films resistors and high speed single pole, double throw switches. This design architecture leads to very low DAC current during normal operation. However, the AUX DACs have a high output impedance (typical 8 k) and hence require external buffering. The AUX DACs have an output voltage range of 0 V to VREF - 1 LSB. Each AUX DAC can be individually entered into lowpower sleep mode, simply by loading all ones or all zeros to that particular AUX DAC. This does not affect the normal operation of AUX DACs, as either of these two codes (all 0s = 0 A, all 1s = 50 A typical) represent the operating points for lowest power consumption.
R R R R R AUX DAC1
the transmit section prior to ramping up (using one of AUX DACs) the RF amplifiers.
AUX DAC DIGITAL INTERFACE
Communication with the auxiliary section is accomplished via a three-pin serial interface, as the timing diagram in Figure 22 illustrates. While AUX LATCH is low, data is clocked into a 16-bit shift register via the AUX DATA and AUX CLK pins. AUX DATA is clocked on the falling edge of AUX CLK, MSB first. The 16-bit shift register is organized as a data field (DB0- DB9) and as a control field (DB10-DB15). The data field is 8-, 9- or 10-bits wide, depending on the AUX DAC being loaded. The control field indicates which AUX DACs are being loaded and also determines the state of the AUX FLAG pin. When the shift register has been loaded, AUX LATCH is brought high to update the selected AUX DACs and the AUX FLAG pin. The control bits are active high, and since a control bit has been assigned to each AUX DAC, this facilitates the simultaneous loading of more than one AUX DAC (with the same data). DB10, DB11 and DB12 selected AUX DAC3, AUX DAC1 and AUX DAC2 respectively, and DBlS determines the logic state of AUX FLAG while DB14 determines whether the three-state driver is enabled.
AUX DAC1 AUX DAC2 AUX DAC3 AUX FLAG
9-BIT AUX DAC1
10-BIT AUX DAC2
8-BIT AUX DAC3
9-BIT AUX LATCH
10-BIT AUX LATCH
8-BIT AUX LATCH
2R
2R
2R
2R
2R
2R
DB0
DB1
DB6
DB7
DB8
AUX LATCH AUX CLK
AUXDAC SELECT 16-BIT SHIFT REGISTER DB0-DB9 DB10 DB11 DB12 DB13
EN
FLAG
DB14
DB15
VREF AGND SHOWN FOR ALL 1s ON DAC
AUX DATA
Figure 21. Auxiliary Section Serial Interface
Figure 20. Auxiliary DAC Structure
The digital AUX FLAG output is available for any external logic control that may be required. For instance, the AUX FLAG could be used to control the Tx SLEEP pin, turning on
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AD7002
VOLTAGE REFERENCE
AUX CLK (I)
The AD7002 contains an on-chip bandgap reference that provides a low noise, temperature compensated reference to the IQ transmit DACs and the IQ receive ADCs. The reference is also made available on the REFOUT pin and can be used to bias other analog circuitry in the IF section. When both the transmit section and the receive section are in sleep mode (Tx SLEEP and Rx SLEEP asserted), the reference output buffer is also powered down by approximately 80% compatible crystal.
t16
AUX DATA (I) DB15 DB14 DB1 DB0
t17 t18
AUX LATCH (I)
t19
t 20
AUX FLAG (O) OLD AUX FLAG NEW AUX FLAG
Figure 22. Auxiliary DAC Timing Diagram
PIN FUNCTION DESCRIPTIONS
PQFP Pin Number Mnemonic POWER SUPPLY 37 AVDD 38 AGND 4, 15 DVDD 5, 16 DGND
Function Positive power supply for analog section. This is +5 V 10%. Analog ground. Positive power supply for digital section. This is +5 V 10%. Digital ground.
ANALOG SIGNAL AND REFERENCE 41 I Tx Analog output for the I (In-Phase) channel. This output comes from a 10-bit DAC and is filtered by a Bessel low pass filter. The 10-bit DAC is loaded with I data, which is generated by the GMSK modulator. 39 Q Tx Analog output for the Q (Quadrature) channel. This output comes from a 10-bit DAC and is filtered by a Bessel low pass filter. The 10-bit DAC is loaded with Q data, which is generated by the GMSK modulator. 44 I Rx Analog input for I receive channel. 42 Q Rx Analog input for Q receive channel. 34 AUX DAC1 Analog output voltage from the 9-bit auxiliary DAC. This is a voltage mode DAC with a high output impedance and hence should be buffered if used to drive moderate impedance loads. 36 AUX DAC2 Analog output voltage from the 10-bit auxiliary DAC. This is a voltage mode DAC with a high output impedance and hence should be buffered if used to drive moderate impedance loads. 35 AUX DAC3 Analog output voltage from the 8-bit auxiliary DAC. This is a voltage mode DAC with a high output impedance and hence should be buffered if used to drive moderate impedance loads. 40 REFOUT Reference output; this is 2.48 volts nominal. TRANSMIT INTERFACE AND CONTROL 7, 11 CLK1, CLK2 Master clock inputs for both the transmit and receive sections. CLK1 and CLK2 must be externally hardwired together and driven from a 13 MHz TTL compatible crystal. 3 Tx CLK Clock output from the AD7002 which can be used to clock in the data for the transmit section. 2 Tx DATA Data input for the transmit section, data is clocked on the falling edge of Tx CLK. 1 Tx SLEEP Sleep control input for transmit section. When it is high, the transmit section goes into standby mode and draws minimal current. RECEIVE INTERFACE AND CONTROL 13 MODE Digital control input. When High (MODE 1), the I and Q outputs are on separate pins (QDATA and IDATA). When Low (MODE 0), I and Q are on the same pin (Rx DATA). 12 RATE Digital control input. This determines whether the receive section interface operates at a word rate of 541.7 kHz or at a word rate of 270.8 kHz. When High (RATE 1), the output word rate is 541.7 kHz. When Low (RATE 0), the output word rate is 270.8 kHz. 18 Rx DATA (IDATA) This is a dual function digital output. When the device is operating in MODE 0, the Rx DATA (both I and Q) is available at this pin. When the device is operating in MODE 1, only IDATA is available at this pin. REV. B -15-
AD7002
PQFP Pin Number 19 Mnemonic I/Q (QDATA) Function This is a dual function digital output. When the device is operating in MODE 0, it indicates whether IDATA or QDATA is present on Rx DATA pin. In MODE 1, QDATA is available at this pin. Synchronization output for framing I and Q data at the receive interface. Output clock for the receive section interface. This digital input controls the output three-state drivers on the receive section interface. When it is High, the outputs are enabled. When Low, they are in high impedance. Calibration control pin for digital filter section. When brought high, for a minimum of 608 master clock cycles, the receive section enters a calibration cycle. Where I and Q offset registers are updated, when the CAL pin is brought low again, with offset values which are subtracted out from subsequent ADC conversions. CAL should remain Low during normal operation. Digital control input. When high the analog modulator input is internally grounded (i.e., tied to VREF). MZERO, in conjunction with CAL, allows on-chip offsets to be calibrated out. Low for normal operation. Power-down control inputs for receive section. When high, the receive section goes into standby mode and draws minimal current. Rx SLEEP1 and Rx SLEEP2 must be externally hardwired together for normal device operation.
23
29
MZERO
27, 24
Rx SLEEP1, Rx SLEEP2
AUXILIARY INTERFACE AND CONTROL 32 AUX LATCH Synchronization input for the auxiliary DACs' shift register and AUX OUT. 31 AUX CLK Clock input for the auxiliary DACs' 16-bit shift register. AUX DATA is latched on the falling edge of AUX CLK while AUX LATCH is low. 30 AUX DATA Data input for the AUX DACs and the AUX FLAG serial interface. 33 AUX FLAG Digital output flag, this can be used as a digital control output and is controlled from the auxiliary serial interface. TEST 8, 26 Test l, Test 2 Test pins for factory use only. These pins should be left unconnected and not used as routes for other circuit signals. 14, 43 Test 3, Test 4 Test pins. These must be tied to ground for normal device operation.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic Quad Flatpack Package (S-44)
0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) 0.548 (13.925) 0.546 (13.875) 0.398 (10.11) 0.390 (9.91) 8 33 34 23 22
0.398 (10.11) 0.390 (9.91)
TOP VIEW
PIN 1 44 1 0.040 (1.02) 0.032 (0.81) 0.083 (2.11) 0.077 (1.96) 0.040 (1.02) 0.032 (0.81) 11 12
0.016 (0.41) 0.012 (0.30)
0.033 (0.84) 0.029 (0.74)
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REV. B
PRINTED IN U.S.A.
0.8
C1700b-0-6/97
20 21 22
Rx SYNC Rx CLK THREE-STATE CONTROL CAL

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